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d a t a sh eet product speci?cation file under integrated circuits, ic02 march 1986 integrated circuits SAA5355 single-chip colour crt controller (ftfrom)
march 1986 2 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 general description the SAA5355 ftfrom (five-two-five-rom) is a single-chip vlsi nmos crt controller capable of handling the display functions required for a 525-line, level-3 videotex decoder. only minimal hardware is required to produce a videotex terminal using ftfrom ? the simplest configuration needs just a microcontroller and 4 kbytes of display memory. features minimal additional hardware required screen formats of 40/80 character by 1-to-25 row display 512 alphanumeric or graphical characters on-chip or extendable off-chip serial attribute storage (stack) and parallel attribute storage dynamically redefinable character (drcs) capability over full field interfaces with 8/16-bit microprocessors with optional direct memory access on-chip scroll map minimizes data to be transferred when scrolling 32 on-screen colours redefinable from a palette of 4096 three on-chip digital-to-analogue converters which compensate for crt non-linearity memory interface capable of supporting multi-page terminals. ftfrom can access up to 128 kbytes of display memory programmable cursor programmable local status row three synchronization modes: stand-alone built-in oscillator operating with an external 6,041957 mhz crystal simple slave directly synchronized from the source of text composite sync phase-locked slave indirect synchronization allows picture-in-text displays (e.g. vcr/vlp video with text overlay) on-chip timing with composite sync output zoom feature which allows the height of any group of rows to be increased to enhance legibility package outline 40-lead dil; plastic (sot129); sot 129-1; 1996 november 18.
march 1986 3 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 fig.1 block diagram.
march 1986 4 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 pinning 1v ss(1) ground (0 v). 2 bufen buffer enable input to the 8-bit link-through buffer. 3 re register enable input. this enables a1 to a6 and uds as inputs, and d8 to d15 as input/outputs. 4 to 19 a16 to a1/ d15 to d0 multiplexed address and data bus input/outputs. these pins also function as the 8-bit link-through buffer. 20 v ss(2) ground (0 v). 21 ref analogue reference input. 22 b analogue outputs (signals are gamma-corrected). 23 g 24 r 25 vds switching output for dot, screen (row), box and window video data; for use when video signal is present (e.g. from tv, vlp, alpha + photographic layer). this output is low for tv display and high for text and will interface directly with a number of colour decoder ics (e.g. tda3563, tda3562a). 26 od output disable causing r, g, b and vds outputs to go to high-impedance state. can be used at dot-rate. 27 clko 12 mhz clock output for hard-copy dot synchronization (referenced to output dots). 28 sand sandcastle feedback output for saa5230 teletext video processor or other circuit. used when the display must be locked to the video source (e.g. vlp). the phase-lock part of the sandcastle waveform can be disabled to allow free-running of the saa5230 phase-locked loop. 29 f1/f6 1,00699 mhz or 6,041957 mhz output. 30 f6 6,041957 mhz clock input (e.g. from saa5230). internal a.c. coupling is provided. 31 vcs/osco video composite sync input (e.g. from saa5230) for phase reference of vertical display timing when locking to a video source (e.g. vlp) or, in stand-alone sync mode, output from internal oscillator circuit (?xed frequency). 32 tcs text composite sync input/output depending on master/slave status. 33 fs/ dda field sync pulse output or de?ned-display-area ?ag output (both referenced to output dots). 34 uds upper data strobe input/output. 35 lds lower data strobe output. 36 dt ack data transfer acknowledge (open drain output). 37 br bus request to microprocessor (open drain output). 38 as address strobe output to external address latches. 39 r/ w( s/r) read/write input/output. also serves as send/receive for the link-through buffer. 40 v dd positive supply voltage ( + 5 v).
march 1986 5 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 ratings limiting values in accordance with the absolute maximum system (iec 134) outputs other than clko, osco, r, g, b, and vds are short-circuit protected. supply voltage range (pin 40) v dd - 0,3 to + 7,5 v maximum input voltage (except f6, tcs, ref) v imax - 0,3 to + 7,5 v maximum input voltage (f6, tcs) v lmax - 0,3 to + 10,0 v maximum input voltage (ref) v ref - 0,3 to + 3,0 v maximum output voltage v omax - 0,3 to + 7,5 v maximum output current i omax 10 ma operating ambient temperature range t amb - 20 to + 70 c storage temperature range t stg - 55 to + 125 c fig.2 pinning diagram.
march 1986 6 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 characteristics v dd = 5 v 5%; v ss = 0 v; t amb = - 20 to + 70 c; unless otherwise speci?ed. parameter symbol min. typ. max. unit supply supply voltage (pin 40) v dd 4,75 5,0 5,25 v supply current (pin 40) i dd -- 350 ma inputs f6 (note 1) slave modes (fig.3) input voltage (peak-to-peak value) v i (p-p) 1,0 - 7,0 v input peaks relative to 50% duty factor v p 0,2 - 3,5 v input leakage current at v i = 0 to 10 v; t amb = 25 ci li -- 20 m a input capacitance c i -- 12 pf stand-alone mode (fig.4) series capacitance of crystal c 1 - 28 - ff parallel capacitance of crystal c 0 - 7,1 - pf resonance resistance of crystal r r -- 60 w gain of circuit g -- note 2 v/v bufen, re, od input voltage low v il 0 - 0,8 v input voltage high v ih 2,0 - 6,5 v input current at v i = 0 to v dd + 0,3 v; t amb = 25 ci i - 10 -+ 10 m a input capacitance c i -- 7pf ref (fig.5) input voltage v ref 0 1 to 2 2,7 v resistance (pin 21 to pin 20) with ref supply and r, g, b outputs off r ref - 125 -w outputs sand output voltage high level at i o = 0 to - 10 m av oh 4,2 - v dd v output voltage intermediate level at i o = - 10 to + 10 m av oi 1,3 2,0 2,7 v output voltage low level at i oh = 0,2 ma v ol 0 - 0,2 v load capacitance c l -- 130 pf
march 1986 7 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 f1/f6, clko, dda/ fs output voltage high at i oh = - 200 m av oh 2,4 - v dd v output voltage low at i ol = 3,2 ma v ol 0 - 0,4 v load capacitance c l -- 50 pf lds, as output voltage high at i oh = - 200 m av oh 2,4 - v dd v output voltage low at i ol = 3,2 ma v ol 0 - 0,4 v load capacitance c l -- 200 pf dt ack, br (open drain outputs) output voltage low at i ol = 3,2 ma v ol 0 - 0,4 v load capacitance c l -- 150 pf capacitance (off state) c off -- 7pf r, g, b (note 3) output voltage high (note 4) at i oh = - 100 m a; v ref = 2,7 v v oh 2,4 -- v output voltage low at i ol = 2 ma v ol -- 0,4 v output resistance during line blanking r obl -- 150 w output capacitance (off state) c off -- 12 pf output leakage current (off state) at v i = 0 to v dd + 0,3 v; t amb = 25 ci off - 10 -+ 10 m a vds output voltage high at i oh = - 250 m av oh 2,4 - v dd v output voltage low at i ol = 2 ma v ol 0 - 0,4 v output voltage low at i ol = 1 ma v ol 0 - 0,2 v output leakage current (off state) at v i = 0 to v dd + 0,3 v; t amb = 25 ci off - 10 -+ 10 m a input/outputs vcs/osco input voltage high v ih 2,0 - 6,0 v input voltage low v il 0 - 0,8 v input current (output off) at v i = 0 to v dd + 0,3 v; t amb = 25 ci i - 10 -+ 10 m a input capacitance c i -- 10 pf load capacitance c l -- 50 pf parameter symbol min. typ. max. unit
march 1986 8 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 tcs input voltage high v ih 3,5 - 10,0 v input voltage low v il 0 - 1,5 v input current at v i = 0 to v dd + 0,3 v; t amb =25 ci i - 10 -+ 10 m a input capacitance c i -- 10 pf output voltage high at i oh = - 200 to 100 m av oh 2,4 - 6,0 v output voltage low at v ol = 3,2 ma v ol 0 - 0,4 v load capacitance c l -- 50 pf a1/d0 to a16/d15, uds, r/ w input voltage low v il 0 - 0,8 v input voltage high v ih 2,0 - 6,0 v input current at v i = 0 to v dd + 0,3 v; t amb =25 ci i - 10 -+ 10 m a input capacitance c i -- 10 pf output voltage high at i oh = - 200 m av oh 2,4 - v dd v output voltage low at i ol = 3,2 ma v ol 0 - 0,4 v load capacitance c l -- 200 pf timing (note 5) f6 (fig.3) rise and fall times t r , t f 10 - 80 ns frequency f f6 5,9 - 6,1 mhz parameter symbol min. typ. max. unit
march 1986 9 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 clko, f1/f6, r, g, b, vds fs/ dda, od (notes 6, 7 and fig.6) clko high time t clkh 25 -- ns clko low time t clkl 15 -- ns clko rise and fall times t clkr t clkf -- 10 ns clko high to r, g, b, vds change t vch 10 -- ns r, g, b, vds valid to clko rise t voc 10 -- ns clko high to r, g, b, vds valid t cov -- 60 ns clko high to r, g, b, vds ?oating after od fall t fod 0 - 30 ns skew between outputs r, g, b, vds t vs -- 20 ns r, g, b, vds rise and fall times t vr , t vf -- 30 ns clko high to r, g, b, vds active after od rise t uod 0 - 60 ns clko high to fs/ dda change t dch 10 - 60 ns fs/ dda valid to clko rise t doc 5 -- ns f1 high time (note 8) t f1h - 500 - ns f1 low time (note 8) t f1l - 500 - ns f6 high time t f6h - 83 - ns f6 low time t f6l - 83 - ns od to clko rise set-up t ods -- 45 ns od to clko high hold t odh -- 0ns memory access timing (notes 9, 10 and fig.7) uds, lds, as cycle time t cyc - 500 - ns uds high to bus-active for address output t saa 75 -- ns address valid set-up to as fall t asu 20 -- ns address valid hold from as low t ash 20 -- ns address ?oat to uds fall t afs 0 -- ns as low to uds fall delay t atd 50 -- ns uds, lds high time t hds 220 -- ns uds, lds low time t lds 200 -- ns as high time t has 125 -- ns as low time t las 320 -- ns parameter symbol min. typ. max. unit
march 1986 10 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 as low to uds high t auh 305 -- ns data valid set-up to uds rise t dsu 30 -- ns data valid hold from uds high t dsh 0 -- ns uds high to as rise delay t uas 0 - 15 ns as low to data valid t afa -- 275 ns link-through buffers (notes 9, 10 and fig.8) bufen low to output valid t bea -- 100 ns link-through delay time t ltd -- 85 ns input data ?oat prior to direction change t ifr 0 -- ns output ?oat after direction change t ofr -- 60 ns output ?oat after bufen high t bed -- 60 ns microprocessor read from ftfrom (fig.9) r/ w high set-up to uds fall t rud 0 -- ns uds low to returned-data access time t uda -- 210 ns re low to returned data access time t rea -- 210 ns data valid to dt ack low delay t dtl 40 -- ns dt ack low to uds rise t dlu 0 -- ns uds high to dt ack rise t dtr 0 - 75 ns uds high to address hold t dsa 10 -- ns uds high to data hold t dsh 10 -- ns uds high to re rise t sre 10 -- ns uds high to r/ w fall t udr 0 -- ns uds low to dt ack low t dsd 250 - 350 ns address valid to uds fall t aul 0 -- ns parameter symbol min. typ. max. unit
march 1986 11 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 notes to the characteristics 1. pin 30 must be biased externally. 2. value under investigation 3. 16-level analogue voltage outputs. 4. output voltage guaranteed when programmed for top level. 5. all timings are related to a 6,00 mhz clock. 6. clko, r, g, b, f1/f6, vds: c l = 25 pf. fs/ dda: c l = 50 pf 7. clko, f1/f6, vds, fs/ dda: reference levels = 0,8 to 2,0 v r, g, b: reference levels = 0,8 to 2,0 v with v ref = 2,7 v 8. these times may momentarily be reduced to a nominal 83 ns in slave-sync mode at the moment of re-synchronization. 9. c l = 150 pf. 10. reference levels = 0,8 to 2,0 v. 11. microprocessor write cycle times of less than 500 ns are permitted but often result in wait states being generated, the precise timing of dtack will then depend on the internal synchronization time. microprocessor write to ftfrom (fig.10) write cycle time (note 11) t wcy 500 -- ns r/ w low set-up to uds fall t wud 0 -- ns re low to uds fall t res 30 -- ns address valid to uds fall t ass 30 -- ns uds low time t lus 100 -- ns data valid to uds rise t dss 80 -- ns uds low to dt ack low t dta 0 - 60 ns uds high to dt ack rise t dtr 0 - 75 ns uds high to data hold t dsh 10 -- ns uds high to address hold t dsa 10 -- ns uds high to re rise t sre 10 -- ns uds high to r/ w rise t udw 0 -- ns f1/f6 to memory access cycle (fig.11) uds high to f6 (component of f1/f6) rise t uf6 20 -- ns f6 (component of f1/f6) high to uds rise t f6u 40 -- ns synchronization and blanking tcs, sand, fs/ dda see fig.12 for timing relationships and fig.13 for vertical sync and blanking waveforms. parameter symbol min. typ. max. unit
march 1986 12 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 fig.3 f6 input waveform. (1) for 525-line operation, frequency = 6,041957 mhz. fig.4 (a) oscillator circuit for SAA5355 stand-alone sync mode and (b) equivalent circuit of crystal at resonance (see characteristics for values). fig.5 circuit arrangement giving one-of-sixteen reference voltage levels for the r, g or b analogue outputs.
march 1986 13 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 fig.6 video timing. fig.7 memory access timing.
march 1986 14 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 fig.8 timing of link-through buffers. fig.9 timing of microprocessor read from ftfrom.
march 1986 15 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 fig.10 timing of microprocessor write to ftfrom. fig.11 timing of f1/f6 to memory access cycle.
march 1986 16 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 fig.12 timing of synchronization and blanking outputs; all timings are nominal and assume f f6 = 6,041957 mhz.
march 1986 17 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 fig.13 vertical synchronization and blanking waveforms; separation of broad pulses = 4,717 m s; equalizing pulse widths = 2,23 m s.
march 1986 18 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 application information more detailed application information is available on request basic videotex decoder configuration a basic, practical decoder configuration is shown in fig.14, reference should also be made to the block diagram fig.1. character and attribute data is fetched from the external memory, processed by the row buffer fill logic according to the stack coding scheme (in stack mode) and then fed into one half of the dual display row buffer. the data fetch process takes place during one line-flyback period (per row) and, since time is required to complete the fill, the other half of the dual row buffer is used for display. the row buffers exchange functions on alternate rows ? each holds the 40 columns of 32 bits required to define explicitly every character in a row. the addresser is used for row buffer filling and for fetching screen colours, and during the display time it is also used for addressing drcs characters. timing the timing chain operates from an external 6,041957 mhz clock or an on-chip fixed-frequency crystal oscillator. the basic video format is 40 characters per row, 20/21 rows per page and 10 video lines per row. ftfrom will also operate with 25 rows per page and 9 video lines per row. the display is generated to the normal 525-line/59,94 hz scanning standard (interlaced or non-interlaced). in addition to composite sync (pin 32) for conventional timebases, a clock output at approximately 1 mhz or 6 mhz (pin 29) is available for driving other devices, and a clock output (pin 27) is available for hard-copy dot synchronization. a de?ned-display-area timing signal (pin 33) simpli?es the application of external peripherals such as a light pen; this signal is nominally coincident with the character dot information. fig.14 basic videotex decoder configuration.
march 1986 19 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 character generation ftfrom supports eight character tables, each of (nominally) 128 characters. four tables are in on-chip rom and contain fixed characters and four are stored in an external ram. the fixed character tables (tables 0 to 3), shown in figs 15 and 16, are applicable to 10-lines-per-row applications. for 9 lines per row applications, the characters will be as shown but with the last line removed from alpha characters and line 5 (labelling 0 to 9) removed from mosaic and line drawing characters. fig.15 on-chip characters: (a) table 0; (b) table 1. (a) (b)
march 1986 20 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 the 128 most commonly used characters are contained in table 0, these are the standard upper and lower-case letters of the roman alphabet, numerals, punctuation and the more common accented characters. in normal text transmission, table 0 is used most of the time. table 1 contains other accented characters. miscellaneous characters, mathematical symbols, the line drawing character set and accents without associated symbols are contained in table 2. table 3 contains the block mosaics for the basic alpha-mosaic service and also the new smooth mosaics. the four tables stored in the external ram (tables 4 to 7) are used for drcs. fig.16 on-chip characters: (a) table 2; (b) table 3. (a) (b)
march 1986 21 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 scroll map the scroll map uses a 26-byte area of on-chip ram and functions in association with the timing chain. it maps the scan row on to the fetched memory row so allowing the stored page to be displayed in any row order. for each row, a 1-byte pointer to the display memory row is stored in the scroll map. this allows scrolling without the need for data transfer to, or from, side storage. additional control bits are stored, allowing 1 to 25 rows to be displayed at any location on the screen. colour map and digital-to-analogue converters the colour map ram contains thirty-two 12-bit words that are loaded by the microprocessor and read out in three 4-bit groups at pixel rate. each group is fed to a non-linear (gamma-corrected) d-a converter. the resulting r, g and b outputs are low-impedance with peak-to-peak amplitudes controlled by the reference voltage applied at pin 21. cursor the cursor is available in the stack mode. its position, character code, character table, foreground colour, background colour, lining and flash attributes are all software programmable via internal register bits. non-videotex applications for non-videotex applications, the device will also support the following operating modes: explicit fill mode. an alternative 40 character/rows mode which does not use the memory compression technique of stack coding. more display memory is required but there are no limitations on the number of display attribute changes per row. 80 characters/rows mode. when operating with 80 characters per row, the available display attributes are eight foreground colours, eight (potentially different) background colours (including transparent) as well as underline and blink. full field drcs mode. this mode is not mutually exclusive to the explicit fill and 80 characters/rows modes but rather the available drcs memory is expanded so that the whole screen can be covered, thus enabling a bit map. all rom-based characters and all display attributes remain available. microprocessor and ram bus interface three types of data transfer take place at the bus interface: ftfrom fetches data from the display memory the microprocessor reads from, or writes to, ftfroms internal register map the microprocessor accesses the display memory ftfrom access to display memory (figs 17 and 18) ftfrom accesses the external display memory via a 16-bit multiplexed address and data bus with a cycle time of 496,5 ns (f6 = 6,041957 mhz). the address strobe ( as) signal from ftfrom flags the bus cycle and writes the address into octal latches (74ls373). the display data is stored in bytes of upper (most-significant) and lower (least-significant) display information and is always fetched in pairs of bytes (upper + lower = 16 bits). the upper and lower display ram sections are enabled simultaneously by the upper and lower data strobes (respectively uds and lds) which are always asserted together to fetch a 16-bit word. the read/write control r/w is included although ftfrom only reads from the display memory.
march 1986 22 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 (1) 74ls373 octal transparent latch (3-state) fig.17 simply ram interface circuit for display memory access. fig.18 bus timing for display memory access.
march 1986 23 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 the display memory organization uses the word/byte addressing convention adopted for the scn68000 microprocessor series. data fetched on the 16-bit bus is considered in terms of bytes where the even numbered bytes use the upper (most-significant) part of the bus as shown in fig.19. the word addresses are numerically the same as the upper byte that they contain - there are no odd-numbered word addresses. warning time as ftfrom is a real-time display device, it must have direct access to the display memory with priority over the microprocessor and other peripheral devices. this is achieved by ftfrom issuing a bus request ( br) signal for the duration of the memory access plus a programmable advance warning time which allows the microprocessor to complete its current bus cycle. in systems where the buses of the microprocessor and ftfrom are intimately connected (connected systems), br may be used to suspend all microprocessor activity so that ftfrom can act as a dedicated dma controller. in systems where the two buses are separated by buffers (disconnected systems), br may be used either to generate an interrupt or as a direct signal. to these ends, the warning time between the assertion of br and the beginning of ftfroms bus activity is programmable to be between 0 and 22,84 m s. fig.19 display memory word/byte organization.
march 1986 24 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 microprocessor access to register map ftfrom has a set of internal registers which, when memory-mapped, behave as an 8-bit wide ram connected to the upper part of the data bus (fig.20). the control signals uds and r/ w are reversed to become inputs and the register map is enabled by the signal re. addresses are input via the lower part of the bus. a data transfer acknowledge signal ( dtack) indicates to the microprocessor that the data transfer is complete. the main data and address paths used in a connected 68000 interface are shown in fig.21. the outputs from the octal latches (74ls373) are enabled only when the 68000 has made the bus available in response to a bus request ( br). when the register map is accessed data is transferred via the upper part of the bus and the microprocessors low-order address is passed to ftfrom via the octal buffers (74ls244). at the same time the bidirectional buffers (74ls245) disable the signals from the low order data bus of the 68000. the buffers 244 and 245 may be omitted in a 16-bit write-only configuration where the least-significant data byte is interpreted by ftfrom as an address. here it will generally be necessary for the microprocessor to hold a (readable) master copy of ftfroms scroll map contents at a location in its main memory. 8-bit microprocessors although the control bus is optimised for the scn68000 16-bit microprocessor unit, ftfrom will operate with a number of widely differing industry-standard 8, 16 or more-bit microprocessors or microcontrollers (e.g. scn68008, mab8051). the interfacing of 8-bit microprocessors to the 16-bit wide display memory is made simple by ftfroms on-chip link-through buffer which provides the microprocessor with bidirectional access to the lower (odd) half of the memory. the link-through buffer is enabled by the buffer-enable signal bufen, and the send/receive direction is controlled by the signal s/r. the main data and address paths used in a connected 8-bit microprocessor system are shown in fig.22. the interface is similar to that of the 16-bit system but here the display memory does not receive a0 as an address, rather a0 is used as the major enabling signal for bufen (enables when high). fig.20 microprocessor access to register map.
march 1986 25 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 (1) 74ls373 octal transparent latch (3-state) (2) 74ls244 octal buffer (3-state) (3) 74ls245 octal transceiver (3-state) (4) scn6800 microprocessor unit fig.21 connected 16-bit microprocessor system.
march 1986 26 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 (1) 74ls373 octal transparent latch (3-state) (2) 74ls244 octal buffer (3-state) fig.22 connected 8-bit microprocessor system.
march 1986 27 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 disconnected systems for many applications it may be desirable to disconnect ftfrom and the display memory from the microprocessor and its rom, ram and other peripherals by using isolating buffers as shown in fig.23. the two parts of the system then operate independently and communicate only when the microprocessor accesses ftfroms register map or the display memory. (1) 74ls373 octal transparent latch (3-state) (2) 74ls244 octal buffer (3-state) (3) 74ls245 octal bus transceiver (3-state) fig.23 disconnected 8-bit system.
march 1986 28 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 synchronization stand-alone mode as a stand-alone device (e.g. in terminal applications) ftfrom can output a composite sync signal ( tcs) to the display timebase ic or to a monitor. timing is obtained from a 6,041957 mhz on-chip oscillator using an external crystal as shown in fig.24. simple-slave in the simple-slave mode ftfrom synchronizes directly to another device as shown in fig.25. ftfroms horizontal counter is reset by the falling edge of tcs. a dead time of 250 ns is built in to avoid resetting the counter at every tv line and so prevents screen jitter. field synchronization is made using ftfroms internal field sync separator. fig.24 stand-alone synchronization mode. fig.25 simple-slave (direct sync) mode.
march 1986 29 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 phase-locked slave the phase-locked slave (indirect sync) mode is shown in fig.26. a phase-locked vco in the saa5230 teletext video processor provides sync to the timebases. when ftfrom is active, its horizontal counter forms part of the phase control loop ? a horizontal reference is fed back to the saa5230 from the sand output and a vertical reference is generated by feeding separated composite sync to ftfroms field sync separator via the vcs input. in the phase-locked slave mode, the display derived from ftfrom can sync with that from a tv source or a local vlp player, thus giving picture-in-text display possibilities. fig.26 phase-locked slave (indirect sync) mode.
march 1986 30 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 package outline unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot129-1 92-11-17 95-01-14 a min. a max. b z max. w m e e 1 1.70 1.14 0.53 0.38 0.36 0.23 52.50 51.50 14.1 13.7 3.60 3.05 0.254 2.54 15.24 15.80 15.24 17.42 15.90 2.25 4.7 0.51 4.0 0.067 0.045 0.021 0.015 0.014 0.009 2.067 2.028 0.56 0.54 0.14 0.12 0.01 0.10 0.60 0.62 0.60 0.69 0.63 0.089 0.19 0.020 0.16 051g08 mo-015aj m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 40 1 21 20 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) (1) dip40: plastic dual in-line package; 40 leads (600 mil) sot129-1
march 1986 31 philips semiconductors product speci?cation single-chip colour crt controller (ftfrom) SAA5355 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). soldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.

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